As a result of technology trends and the increased importance of portable electronic devices, leakage (static) power dissipation has emerged as a high priority design consideration in high-performance processor design. Historically, architectural innovations for improving performance relied on exploiting ever larger numbers of transistors operating at higher frequencies. To keep the higher resulting switching power dissipation at bay, successive technology generations have relied on reducing the supply voltage. In order to maintain performance, however, this has required a corresponding reduction in the transistor threshold voltage. Since the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) sub-threshold leakage current increases exponentially with a reduced threshold voltage, leakage power dissipation has grown to be a significant fraction of overall chip power dissipation in modern, deep-submicron (<0.18 pm) processes. Moreover, it is expected to grow by a factor of five every newer chip generation. For processors it is estimated that in 0.1 μm technology, leakage power will account for about 50% of the total chip power.
Since leakage power is proportional to the number of transistors, and given the projected large memory content of future System-on-Chip (SOC) devices, it becomes important to focus on Static Random Access Memory (SRAM) structures such as caches, which comprise the vast majority of on-chip transistors in some systems. Existing circuit-level leakage reduction techniques are oblivious to program behavior, such as how many bits to be stored will be high or low, and trade off performance for reduced leakage where possible. Combined circuit and architecture-level techniques reduce leakage for those parts of the on-chip caches that remain unused for long periods of time (for example, such as for thousands of cycles). The mechanisms that identify which cache parts will be unused and that enable leakage reduction incur considerable power and performance overheads that have to be amortized over long periods of time. As a result, these methods are not effective when most of the cache is actively used.
There is a need for SRAM storage with reduced leakage power while having comparable performance characteristics. As such, power consumption may be minimized while still providing the performance required in new generation systems and consumer devices.